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CH7301A
CHRONTEL
Chrontel CH7301 DVI Output Device
Features
* * * * * * * * * * DVI Transmitter up to 165MHz DVI low jitter PLL DVI hot plug detection Provides 10-bit high speed video DAC for RGB output DAC connection detect Programmable power management Fully programmable through I 2 C port Complete Windows and DOS driver support Low voltage interface support to graphics device Offered in a 64-pin LQFP package
General Description
The CH7301 is a Display controller device which accepts a digital graphics input signal, and encodes and transmits data through a DVI (TMDSTM link) or DFP (Digital flat panel) can also be supported. The device accepts data over one 12-bit wide variable voltage data port which supports four different RGB data formats. The DVI processor includes a low jitter PLL for generation of the high frequency serialize clock, and all circuitry required to encode, serialize and transmit data. The CH7301 comes in versions able to drive a DFP display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device.
XCLK,XCLK*
Clock Driver DVI Encode
DVI (TMDS TM link) PLL DVI Serialize DVI Driver
TLC,TLC* TDC0,TDC0* TDC1,TDC1* TDC2,TDC2* VSWING Three 8-bit DAC's R G B
D[11:0]
12
Data Latch, Demux
H,V,DE VREF
3
H,V,DE Latch
ISET IIC Control C/H SYNC
HPDET GPIO[1:0] TLDET*
AS
SC
SD
BCO
RESET*
Figure 1: Functional Block Diagram
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Pin Descriptions
Package Diagram
CH7301A
XCLK*
DGND
DVDD DE VREF H V DGND GPIO[1] / TLDET* GPIO[0] HPDET AS DGND DVDD RESET* SD SC AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DVDD
XCLK
D[10]
D[11]
D[0] D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8] D[9]
C / H SYNC BCO TLDET* DVDDV AVDD NC GND AGND GND B R G NC ISET GND VDD
Chrontel CH7301
TDC0
TDC1
TGND
TGND
TDC2 TVDD
TLC
TDC0*
TDC1*
AVDD VSWING
Figure 2: 64-Pin LQFP
2
TDC2*
AGND
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TGND
TVDD
TLC*
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CHRONTEL
Table 1: Pin Description 64-Pin # Pins Type LQFP
2 1 In
CH7301A
Symbol
DE
Description
Data Enable
This pin accepts a data enable signal which is high when active video data is input to the device, and low all other times. The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. This input is used by the DVI links.
3
1
In
VREF
Reference Voltage Input
The VREF pin inputs a reference voltage of DVDDV / 2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync, data enable and clock inputs.
4 5 7
1 1 2
In/Out In/Out In/Out
H V GPIO[1] / TLDET*
Horizontal Sync Input / Output
This output is only for use with the TV-Out function.
Vertical Sync Input / Output
This output is only for use with the TV-Out function.
General Purpose Input - Output[1] / DVI Link Detect Output (internal pull-up)
This pin provides a general purpose I/O controlled via the IIC bus. The internal pull-up will be to the DVDD supply. When the GPIO[1] pin is configured as an input, this pin can be used to output the DVI link detect signal (pulls low when a termination change has been detected on the HPDET input). This is an open drain output. The output is released through IIC control.
8
2
In/Out
GPIO[0]
General Purpose Input - Output[0] (internal pull-up)
This pin provides a general purpose I/O controlled via the IIC bus. The internal pull-up will be to the DVDD supply.
9
1
In
HPDET
Hot Plug Detect (internal pull-down)
This input pin determines whether the TMDSTM link is connected to a DVI monitor. When terminated, the monitor is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via the P-Out/TLDET* or GPIO[1]/TLDET* pin pulling low.
10
1
In
AS
Address Select (Internal pull-up)
This pin determines the IIC address of the device (1,1,1,0,1,AS*,AS).
13
1
In
RESET*
Reset * Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the IIC register.
14
1
In/Out
SD
Serial Data Input / Output
This pin functions as the serial data pin of the IIC interface port, and uses the DVDD supply.
15
1
In
SC
19
1
In
VSWING
Serial Clock Input This pin functions as the clock pin of the IIC interface port, and uses the DVDD supply. DVI Link Swing Control
This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor should be connected between this pin and TGND using short and wide traces.
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Table 1: Pin Description 64-Pin # Pins Type LQFP
22, 21 2 Out
CH7301A
Symbol
TDC0, TDC0*
Description
TMDS TM Data Channel 0 Outputs
These pins provide the TMDSTM differential outputs for data channel 0 (blue).
25, 24
2
Out
TDC1, TDC1*
TMDS TM Data Channel 1 Outputs
These pins provide the TMDSTM differential outputs for data channel 1 (green).
28, 27
2
Out
TDC2, TDC2*
TMDS TM Data Channel 2 Outputs
These pins provide the TMDSTM differential outputs for data channel 2 (red).
30, 31
2
Out
TLC, TLC*
TMDS TM Link Clock Outputs
These pins provide the differential clock output for the TMDSTM interface corresponding to data on the TDC[0:2] outputs.
35
1
In
ISET
Current Set Resistor Input
This pin sets the DAC current. A 140 ohm resistor should be connected between this pin and GND (DAC ground) using short and wide traces.
37 38 39 43 46
1 1 1 1 1
Out Out Out Out
G R B NC TLDET*
Green Output Red Output Blue Output No Connect DVI Link Detect Output
This pin provides an open drain output which pulls low when a termination change has been detected on the HPDET input. The output is released through IIC control.
47
1
Out
BCO
Buffered Clock Output
This output pin provides a buffered clock output, driven by the DVDD supply. The output clock can be selected using the BCO register.
48 50 - 55, 58 - 63 57, 56
1 12
Out In
C/H SYNC
Composite / Horizontal Sync Output
This pin is only for use with the TV-Out function.
D[11] - D[0] Data[11] through Data[0] Inputs
2
In
XCLK, XCLK*
These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. External Clock Inputs These inputs form a differential clock signal input to the CH7301 for use with the H, V, DE and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The output clocks from this pad cell are able to have their polarities reversed under the control of the MCP bit. Digital Supply Voltage (3.3V) Digital Ground I/O Supply Voltage (3.3V - 1.1V) DVI Transmitter Supply Voltage (3.3V) DVI Transmitter Ground PLL Supply Voltage (3.3V) PLL Ground DAC Supply Voltage (3.3V) DAC Ground
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1, 12, 49 6, 11, 64 45 23, 29 20, 26, 32 18, 44 16, 17, 41,42 33 34, 36, 40 4
3 3 1 2 3 2 4 1 3
Power Power Power Power Power Power Power Power Power
DVDD DGND DVDDV TVDD TGND AVDD AGND VDD GND
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Mode of Operation
CH7301A
The CH7301 is capable of being operated as a single DVI output link. Descriptions of the single DVI output link operating mode, with a block diagram of the data flow within the device is shown below.
DVI Output
In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7301 from the graphics controllers digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the pixel rate. Some examples of modes supported are shown in the table below, and a block diagram of the CH7301 is shown on the following page. For the table below, clock frequencies for given modes were taken from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications. Any values of pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below 165MHz. For correct DVI operation, the input data format must be selected to be one of the RGB input formats.
Table 2: DVI Output
Graphics Resolution 720x400 640x400 640x480 720x4801 720x5761 800x600 1024x768 1280x720 1280x1024 1600x1200 1920x1080
1 2
Active Aspect Ratio 4:3 8:5 4:3 4:3 4:3 4:3 4:3 16:9 4:3 4:3 16:9
Pixel Aspect Refresh Rate Ratio 1.35:1.00 1:1 1:1 9:8 15:12 1:1 1:1 1:1 1:1 1:1 1:1 (Hz) <85 <85 <85 59.94 50 <85 <85 <60 <85 <60 <302
XCLK
DVI
Frequency Frequency (MHz) <35.5 <31.5 <36 27 27 <57 <95 <67 <158 <165 <140 (MHz) <355 <315 <360 270 270 <570 <950 <670 <1580 <1650 <1400
These DVD compatible modes are input in a non-interlaced RGB data format 30Hz in progressive scan modes, 60Hz in interlaced modes
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CH7301A
XCLK,XCLK*
Clock Driver DVI Encode
DVI (TMDSTM link) PLL DVI Serialize DVI Driver
TLC,TLC* TDC0,TDC0* TDC1,TDC1* TDC2,TDC2* VSWING Three 8-bit DAC's CVBS (DAC3) Y (DAC 1) C (DAC 2) CVBS (DAC0) ISET
D[11:0]
12
Data Latch, Demux
H,V,DE VREF HPDET GPIO[1:0] TLDET* AS SC SD BCO RESET*
3
H,V,DE Latch
C/H SYNC
IIC Control
Figure 3: DVI Output
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Input Interface
Two distinct methods of transferring data to the CH7301 are described. They are: * Multiplexed data, clock input at 1X pixel rate * Multiplexed data, clock input at 2X pixel rate
CH7301A
For the multiplexed data, clock at 1X pixel rate the data applied to the CH7301 is latched with both edges of the clock (also referred to as dual-edge transfer mode). For the multiplexed data, clock at 2X pixel rate the data applied to the CH7301 is latched with one edge of the clock. The polarity of the pixel clock can be reversed under IIC control.
Input Clock and Data Timing Diagram
The figure below shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform represents the input clock for the multiplexed data, clock at 2X pixel rate method. The second XCLK/XCLK* waveform represents the input clock for the multiplexed data, clock at 1X pixel rate method.
VOH VOL VOH VOL t1 t2 VOH
XCLK/ XCLK* XCLK/ XCLK* D[11:0]
VOL VOH
DE
VOL t1 VOH t2 64 P-OUT VOL VOH
H
V
VOL
1 VGA Line
Figure 4: Interface Timing
Table 3: Interface Timing Symbol Parameter V OH Output high level of interface signals V OL Output Low level of interface signals 1 D[11:0], H, V & DE to XCLK = XCLK* Delay (setup t1 time)
XCLK = XCLK* to D[11:0], H, V & DE Delay (hold time) DVDDV Digital I/O Supply Voltage t21
1
Min
DVDDV - 0.2 -0.2 TBD
Max
DVDDV + 0.2 0.2
Unit
V V nS
TBD 1.1 - 5% 3.3 + 5%
nS V
D[11:0], H, V DE times measured when input equals Vref+100mV on rising edges, Vref-100mV on falling edges.
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Input Clock and Data Formats
CH7301A
The 12 data inputs support 5 different multiplexed data formats, each of which can be used with a 1X clock latching data on both clock edges, or a 2X clock latching data with a single edge. The data received by the CH7301 can be used to drive the DVI output or directly drive the DAC's. The multiplexed input data formats are (IDF[2:0]):
IDF 0 1 2 3 4
Description 12-bit multiplexed RGB input (24-bit color), (multiplex scheme 1) 12-bit multiplexed RGB2 input (24-bit color), (multiplex scheme 2) 8-bit multiplexed RGB input (16-bit color, 565) 8-bit multiplexed RGB input (15-bit color, 555) 8-bit multiplexed YCrCb input (24-bit color), (Y, Cr and Cb are multiplexed)
For multiplexed input data formats, either both transitions of the XCLK/XCLK* clock pair, or each rising or falling edge of the clock pair (depending upon MCP bit, rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal) will latch data from the graphics chip. The multiplexed input data formats are shown in the figures below. The Pixel Data bus represents a 12-bit or 8-bit multiplexed data stream, which contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate, and each pair of Pn values (eg; P0a and P0b) will contain a complete pixel encoded as shown in the tables below. It is assumed that the first clock cycle following the leading edge of the incoming horizontal sync signal contains the first word (Pxa) of a pixel, if an active pixel was present immediately following the horizontal sync. This does not mean that active data should immediately follow the horizontal sync, however. When the input is a YCrCb data stream the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples and the following Y1 byte refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active pixels should be 0 in RGB formats, and 16 for Y and 128 for CrCb in YCrCb formats.
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HS XCLK
(2X)
CH7301A
SAV
XCLK
(1X)
D[11:0] The following data is latched for IDF = 0 P[23:16]
(Red Data)
P0a
P0b
P1a
P1b
P2a
P2b
P0b[11:4]
P1b[11:4]
P2b[11:4]
P[15:8]
(Green Data)
P0b[3:0], P0a[11:8]
P1b[3:0], P1a[11:8]
P2b[3:0], P2a[11:8]
P[7:0]
(Blue Data)
P0a[7:0]
P1a[7:0]
P2a[7:0]
The following data is latched for IDF = 1 P[23:16]
(Red Data) P0b[11:7], P0b[3:1] P1b[11:7], P1b[3:1] P2b[11:7] P2b[3:1]
P[15:8]
(Green Data)
P0b[6:4], P0a[11:9], P0b[0], P0a[3]
P1b[6:4], P1a[11:9], P1b[0], P1a[3] P2a[8:4] P2a[2:0]
P[7:0]
(Blue Data)
P0a[8:4], P0a[2:0]
P1a[8:4], P1a[2:0]
Figure 5: Multiplexed Input Data Formats (IDF = 0, 1)
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HS XCLK
(2X)
CH7301A
SAV
XCLK
(1X)
D[11:0] The following data is latched for IDF = 2 P[23:19]
(Red Data)
P0a
P0b
P1a
P1b
P2a
P2b
P0b[11:7]
P1b[11:7]
P2b[11:7]
P[15:10]
(Green Data)
P0b[6:4], P0a[11:9]
P1b[6:4], P1a[11:9]
P2b[6:4], P2a[11:9]
P[7:3]
(Blue Data)
P0a[8:4]
P1a[8:4]
P2a[8:4]
The following data is latched for IDF = 3 P[23:19]
(Red Data) P0b[10:6] P1b[10:6] P2b[10:6]
P[15:11]
(Green Data)
P0b[5:4], P0a[11:9]
P1b[5:4], P1a[11:9]
P2b[5:4], P2a[11:9]
P[7:3]
(Blue Data)
P0a[8:4]
P1a[8:4]
P2a[8:4]
The following data is latched for IDF = 4 CRA
(internal signal)
P[23:16]
(Y Data)
P0b[7:0]
P1b[7:0]
P2b[7:0]
P[15:8]
(CrCb Data)
P0a[7:0]
P1a[7:0]
P2a[7:0]
P[7:0]
(ignored)
GND
GND
GND
Figure 6: Multiplexed Input Data Formats (IDF = 2, 3, 4)
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Table 4: Multiplexed Input Data Formats (IDF = 0, 1)
IDF = Format = Pixel # Bus Data P0a G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] 0 12-bit RGB (12-12) P0b P1a R0[7] G1[3] R0[6] G1[2] R0[5] G1[1] R0[4] G1[0] R0[3] B1[7] R0[2] B1[6] R0[1] B1[5] R0[0] B1[4] G0[7] B1[3] G0[6] B1[2] G0[5] B1[1] G0[4] B1[0] P1b R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] P0a G0[4] G0[3] G0[2] B0[7] B0[6] B0[5] B0[4] B0[3] G0[0] B0[2] B0[1] B0[0] 1
CH7301A
D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
12-bit RGB (12-12) P0b P1a R0[7] G1[4] R0[6] G1[3] R0[5] G1[2] R0[4] B1[7] R0[3] B1[6] G0[7] B1[5] G0[6] B1[4] G0[5] B1[3] R0[2] G1[0] R0[1] B1[2] R0[0] B1[1] G0[1] B1[0]
P1b R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6] G1[5] R1[2] R1[1] R1[0] G1[1]
Table 5: Multiplexed Input Data Formats (IDF = 2, 3)
IDF = Format = Pixel # Bus Data P0a G0[4] G0[3] G0[2] B0[7] B0[6] B0[5] B0[4] B0[3] 2 RGB 5-6-5 P0b P1a R0[7] G1[4] R0[6] G1[3] R0[5] G1[2] R0[4] B1[7] R0[3] B1[6] G0[7] B1[5] G0[6] B1[4] G0[5] B1[3] P1b R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6] G1[5] P0a G0[5] G0[4] G0[3] B0[7] B0[6] B0[5] B0[4] B0[3] 3 RGB 5-5-5 P0b P1a X G1[5] R0[7] G1[4] R0[6] G1[3] R0[5] B1[7] R0[4] B1[6] R0[3] B1[5] G0[7] B1[4] G0[6] B1[3] P1b X R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6]
D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4]
Table 6: Multiplexed Input Data Formats (IDF = 4)
IDF = Format = Pixel # Bus Data P0a Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] P0b Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] P1a Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] 4 YCrCb 8-bit P1b P2a Y1[7] Cb2[7] Y1[6] Cb2[6] Y1[5] Cb2[5] Y1[4] Cb2[4] Y1[3] Cb2[3] Y1[2] Cb2[2] Y1[1] Cb2[1] Y1[0] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
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CH7301A
When IDF = 4 (YCrCb mode), the data inputs can also be used to transmit sync information to the device. In this mode, the embedded sync will follow the VIP2 convention, and the first byte of the `video timing reference code' will be assumed to occur when a Cb sample would occur, if the video stream was continuous. This is shown below:
Table 7: Embedded Sync
IDF = Format = Pixel # Bus Data P0a FF FF FF FF FF FF FF FF P0b 00 00 00 00 00 00 00 00 P1a 00 00 00 00 00 00 00 00 4 YCrCb 8-bit P1b P2a S[7] Cb2[7] S[6] Cb2[6] S[5] Cb2[5] S[4] Cb2[4] S[3] Cb2[3] S[2] Cb2[2] S[1] Cb2[1] S[0] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
Dx[7] Dx[6] Dx[5] Dx[4] Dx[3] Dx[2] Dx[1] Dx[0]
In this mode, the S[7..0] byte contains the following data: S[6] S[5] S[4] = = = F V H = = = 1 during field 2, 0 during field 1 1 during field blanking, 0 elsewhere 1 during EAV (synchronization reference at the end of active video) 0 during SAV (synchronization reference at the start of active video) Bits S[7] and S[3..0] are ignored
Hot Plug Detection
The CH7301 has the capability of signaling to the graphics controller when the termination of the DVI outputs has changed. The operation of this circuit is as follows. The HPDET input pin of the CH7301 should be connected to pin 16 of the DVI connector. When a DVI monitor is connected to the DVI connector, this pin will be pulled high (above 2.4 volts). When a DVI monitor is not connected to the DVI connector, the internal pull-down on the HPDET pin will pull low. The CH7301 will detect any transition at the HPDET pin. When the HPIE (Hot Plug Interrupt Enable) bit in IIC register 1Eh is high, the CH7301 will pull low on the P-Out / TLDET* pin. When the HPIE2 (Hot Plug Interrupt Enable 2) bit in IIC register 20h is high, the CH7301 will pull low on the GPIO[1] / TLDET* pin. This should signal the driver to read the DVIT bit in register 20h to determine the state of the HPDET pin. The P-Out / TLDET* pin will continue to pull low until the driver sets the HPIR (Hot Plug Interrupt Reset) bit in register 1Eh high. The driver should then set the HPIR bit low.
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Register Control
CH7301A
The CH7301 is controlled via an IIC control port. The IIC bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device retains all register states The CH7301 contains a total of 37 registers for user control.
Control Registers Map
The controls are listed below, divided into three sections: general controls, input / output controls and DVI controls. A register map and register description follows.
GENERAL CONTROLS
ResetIB ResetDB PD[6:0] VID[7:0] DID[7:0] TSTP[1:0] Software IIC reset Software datapath reset Power down controls (DVIP, DVIL, , DACPD[2:0], Full, Partial) Version ID register Device ID register Enable/select test pattern generation (color bar, ramp)
INPUT/OUTPUT CONTROLS
XCM XCMD[7:0] MCP HPIE, HPIE2 HPIR IDF[2:0] IBS TERM[5:0] BCOEN BCO[2:0] BCOP GPIOL[1:0] GOENB[1:0] SYNCO[1:0] DACG[1:0] DACBP XCLK 1X, 2X select Delay adjust between XCLK and D[11:0] XCLK polarity control Hot plug detect interrupt enable Hot plug detect interrupt reset Input data format Input buffer select Termination detect/check (DVI Link, DACT3, DACT2, DACT1, DACT0, SENSE) Enable BCO Output Select output signal for BCO pin BCO polarity Read or write level for GPIO pins Direction control for GPIO pins Enables/selects sync output for bypass modes DAC gain control DAC bypass
DVI CONTROLS
TPPD[2:0] TPCP[1:0] TPVT[5:0] TPVCO[10:0] TPLPF[3:0] DVID[3:0] DVII CTL[3:0] DVI PLL phase detector trim DVI PLL charge pump trim DVI PLL VDD trim DVI PLL VCO trim DVI PLL low pass filter DVI transmitter drive strength DVI output invert DVI control inputs
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I2C Port Operation
CH7301A
The CH7301 contains a standard I2C control port, through which the control registers can be written and read. This port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to the SDB and SCB buses as shown in Figure 7. The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in Figure 7). The CH7301 acts as a slave, and generation of clock signals on the bus is always the responsibility of the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to 400 kbit/s.
+DVDD RP
SDB (Serial Data Bus) SCB (Serial Clock Bus) SC DATAN2 OUT MASTER SCLK OUT FROM MASTER SD
DATAN2 OUT
DATAN2 OUT
DATA IN MASTER
SCLK IN1
DATA IN1
SCLK IN2
DATA IN2
BUS MASTER
SLAVE
SLAVE
Figure 7: Connection of Devices to the Bus
Electrical Characteristics for Bus Devices
The electrical specifications of the bus devices' inputs and outputs and the characteristics of the bus lines connected to them are shown in Figure 7. A pull-up resistor (RP) must be connected to a 3.3V 10% supply. The CH7301 is a device with input levels related to DVDD. Maximum and minimum values of pull-up resistor (RP ) The value of RP depends on the following parameters: * Supply voltage * Bus capacitance * Number of devices connected (input current + leakage current = Iinput ) The supply voltage limits the minimum value of resistor RP due to the specified minimum sink current of 2mA at VOLmax = 0.4 V for the output stages: RP >= (V DD - 0.4) / 2 (R P in k) The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of RP due to the specified rise time. The equation for RP is shown below: RP <= 103 /C (where: RP is in k and C, the total capacitance, is in pF) The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 A. Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of RP. The RP limit depends on V DD and is shown below: RP <= (100 x V DD)/ Iinput (where: RP is in k and Iinput is in A)
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Transfer Protocol
CH7301A
Both read and write cycles can be executed in "Alternating" and "Auto-increment" modes. Alternating mode expects a register address prior to each read or write from that location (i.e., transfers alternate between address and data). Auto-increment mode allows you to establish the initial register location, then automatically increments the register address after each subsequent data access (i.e., transfers will be address, data...). A basic serial port transfer protocol is shown in Figure 8 and described below.
SD
I2C
SC
CH7301
8
9
1-8
9
1-8
9
Start Condition
Device ID
R/W*
ACK
CH7301 acknowledge
Data1
ACK
CH7301 acknowledge
Data n
CH7301 acknowledge
ACK
Stop Condition
Figure 8: Serial Port Transfer Protocol 1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the "START" condition. Transitions of address and data bits can only occur while SC is low. 2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the "STOP" condition. 3. Upon receiving the first START condition, the CH7301 expects a Device Address Byte (DAB) from the master device. The value of the device address is shown in the DAB data format below. 4. After the DAB is received, the CH7301 expects a Register Address Byte (RAB) from the master. The format of the RAB is shown in the RAB data format below (note that B7 is not used).
Device Address Byte (DAB)
B7
1
B6
1
B5
1
B4
0
B3
1
B2
0
B1
1
B0
R/W
R/W
Read/Write Indicator
"0": "1":
master device will write to the CH7301 at the register location specified by the address AR[6:0] master device will read from the CH7301 at the register location specified by the address AR[6:0].
Register Address Byte (RAB)
B0
AR[0]
B7
1
B6
AR[6]
B5
AR[5]
B4
AR[4]
B3
AR[3]
B2
AR[2]
B1
AR[1]
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Transfer Protocols (continued)
AAR[6:0] Specifies the Address of the Register to be Accessed.
CH7301A
This register address is loaded into the Address Register of the CH7301. The R/W access, which follows, is directed to the register specified by the content stored in the Address Register. The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and AutoInc and alternating operation.
CH7301 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the mastertransmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slavereceiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the HIGH period of the clock pulse. The CH7301 always acknowledges for writes (see Figure 9). Note that the resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
SD Data Output By Master-Transmitter not acknowledge SD Data Output By the CH7301 SC from Master Start Condition 1 2
acknowledge 8 9
clock pulse for acknowledgment
Figure 9: Acknowledge on the Bus
Figure 10 shows two consecutive alternating write cycles. The byte of information, following the Register Address Byte (RAB), is the data to be written into the register specified by AR[6:0]. If AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.
SD
CH7301 acknowledge
CH7301 acknowledge
CH7301 acknowledge
CH7301 acknowledge
CH7301 acknowledge
I2 C
SC
1-7
8
9
1-8
9
1-8
9
1-8
9
1-8
9
Start Condition
Device ID
R/W*
ACK
RAB
ACK
Data
ACK
RAB
ACK
Data
ACK
Stop Condition
Note: The acknowledge is from the CH7301 (slave).
Figure 10: Alternating Write Cycles
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CH7301A
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle is shown in Figure 11. .
CH7301 acknowledge CH7301 acknowledge CH7301 acknowledge CH7301 acknowledge
SD
I2 C
SC
1-7
8
9
1-8
9
1-8
9
1-8
9
Start Condition
Device ID
R/W*
ACK
RAB n
ACK
Data n
ACK
Data n+1
ACK
Stop Condition
Note: The acknowledge is from the CH7301 (slave).
Figure 11: Auto-Increment Write Cycle During auto-increment mode transfers, the register address pointer continues to increment for each write cycle until AR[6:0] = 4F. The next byte of information represents a new auto-sequencing "Starting address", which is the address of the register to receive the next byte. The auto-sequencing then resumes based on this new "Starting address". The auto-increment sequence can be terminated any time by either a "STOP" or "RESTART" condition. The write operation can be terminated with a "STOP" condition.
CH7301 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7301 releases the data line to allow the master to generate the STOP condition or the RESTART condition. To read the content of the registers, the master device starts by issuing a "START" condition (or a "RESTART" condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB with AR[6:0], containing the address of the register that the master device intends to read from in AR[6:0]. The master device should then issue a "RESTART" condition ("RESTART" = "START", without a previous "STOP" condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the master's intention to read data hereafter. The master then reads the next byte of data (the content of the register specified in the RAB). For alternating modes, another RESTART condition, followed by another DAB with R/W = 0 and RAB, is expected from the master device. The master device then issues another RESTART, followed by another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition, followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read events. Two consecutive alternating read cycles are shown in Figure 12.
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Transfer Protocols (continued)
.
CH7301 acknowledge CH7301 acknowledge CH7301 acknowledge
CH7301A
SD
Master does not acknowledge
I 2C
I2 C
SC Start Condition
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
10
Device ID R/W*
ACK
RAB 1
ACK
Restart Condition
Device ID R/W*
ACK
Data 1
ACK
Restart Condition
Master does not acknowledge CH7301 acknowledge CH7301 acknowledge CH7301 acknowledge
I2 C
I2 C
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
Device ID
R/W*
ACK
RAB 2
ACK
Restart Device ID Condition
R/W*
ACK
Data 2
ACK
Stop Condition
Figure 12: Alternating Read Cycle For auto-increment reads the address register will be incremented automatically and subsequent data bytes can be read from successive registers, without providing a second RAB.
CH7301 acknowledge
CH7301 acknowledge
CH7301 acknowledge
Master acknowledge
Master does not acknowledge just before Stop condition
SD
I 2C
SC
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
1-8
9
Start Device ID R/W* Condition
ACK
RAB n
ACK
Restart Device ID R/W* Condition
ACK
Data n
ACK
Data n+1
ACK
Stop Condition
Figure 13: Auto-increment Read Cycle When the auto-increment mode is enabled, the Address Register will continue incrementing for each read cycle. When the content of the Address Register reaches 4Fh, it will wrap around and start from 00h again. The auto increment sequence can be terminated by either a "STOP" or "RESTART" condition. The read operation can be terminated with a "STOP" condition. Figure 13 shows an auto-increment read cycle terminated by a STOP or RESTART condition.
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Table 8: IIC Register Map w/o Macrovision
Register 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 31h 32h 33h 35h 36h 37h 48h 49h 4Ah 4Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Reserved XCMD3 HPIR Reserved DACT2 SYNCO0 BCOP CTL3 TPVCO3 TPVT3 Bit 2 MCP XCMD2 HPIE IDF2 DACT1 DACG1 BCO2 CTL2 TPVCO2 TPVT2 Bit 1 Reserved XCMD1 Reserved IDF1 DACT0 DACG0 BCO1 CTL1 TPVCO1 TPCP1 TPVT1
CH7301A
Bit 0 XCM XCMD0 Reserved IDF0 SENSE DACBP BCO0 CTL0 TPVCO0 TPCP0 TPVT0
GOENB1 IBS HPIE2 Reserved Reserved TPPD3 TPVCO7 DVID2 TPLPF3 TPVCO10 DVIP VID7 DID7
GOENB0 Reserved Reserved Reserved Reserved TPPD2 TPVCO6 DVID1 TPLPF2 TPVCO9 DVIL VID6 DID6
GPIOL1 Reserved DVIT Reserved TPPD1 TPVCO5 DVID0 TPVT5 TPLPF1 TPVCO8 Reserved VID5 DID5
GPIOL0 Reserved SYNCO1 BCOEN TPPD0 TPVCO4 DVII TPVT4 TPLPF0 ResetIB DACPD3 VID4 DID4
ResetDB DACPD2 VID3 DID3
RSA DACPD1 VID2 DID2
TSTP1 DACPD0 VID1 DID1
TSTP0 FPD VID0 DID0
All register bits not defined in the register map are reserved bits, and should be left at the default value.
Clock Mode Register
Symbol: Address: Bits:
CM 1Ch 2
BIT: SYMBOL: TYPE: DEFAULT:
7
6
5
4
3 Reserved R/W 0
2 1 MCP Reserved R/W R/W 0 0
0 XCM R/W 0
Bit 0 of register CM signifies the XCLK frequency. A value of `0' is used when the XCLK is at the pixel frequency (duel edge clocking mode) and a value of `1' is used when the XCLK is twice the pixel frequency (single edge clocking mode). Bit 2 of register CM controls the phase of the XCLK clock input to the CH7301. A value of `1' inverts the XCLK signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching input data.
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Input Clock Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
CH7301A
IC 1Dh 8
7 6 5 4 3 2 1 Reserved Reserved Reserved Reserved XCMD3 XCMD2 XCMD1 R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 1 0 0
0 XCMD0 R/W 0
Bits 3-0 of register IC controls the delay applied to the XCLK signal before latching input data.
GPIO Control Register
Symbol: Address: Bits:
GPIO 1Eh 8
BIT: SYMBOL: TYPE: DEFAULT:
7 6 5 4 GOENB1 GOENB0 GPIOL1 GPIOL0 R/W R/W R/W R/W 1 1 0 0
3 HPIR R/W 0
2 1 HPIE Reserved R/W R/W 0 0
0 Reserved R/W 0
Bit 2 of register GPIO enables the hot plug interrupt detection signal to be output from the P-Out pin. A value of `1' allows the hot plug detect circuit to pull the TLDET* pin low when a change of state has taken place on the hot plug detect pin. A value of `0' disables the interrupt signal. Bit 3 of register GPIO resets the hot plug detection circuitry. A value of `1' causes the CH7301 to release the TLDET* pin. When a hot plug interrupt is asserted by the CH7301, the CH7301 driver should read register 20h to determine the state of the DVI termination. After having read this register, the HPIR bit should be set high to reset the circuitry, and then set low again. Bits 5-4 of register GPIO control the GPIO pins. When the corresponding GOENB bits are low, these register values are driven out of the corresponding GPIO pins. When the corresponding GOENB bits are high, these register values can be read to determine the level forced into the corresponding GPIO pins. Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of `1' sets the corresponding GPIO pin to an input, and a value of `0' sets the corresponding pin to an output.
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Input Data Format Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
CH7301A
IDF 1Fh 8
7 IBS R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 IDF2 R/W 0
1 IDF1 R/W 0
0 IDF0 R/W 0
Bits 2-0 of register IDF select the input data format. See Input Interface on page 5 for a listing of available formats. Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins. Connection Detect Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
CD 20h 6
7 6 HPIE2 Reserved R/W R/W 0 0
5 4 DVIT Reserved R R 0 0
3 DACT2 R 0
2 DACT1 R 0
1 DACT0 R 0
0 SENSE R/W 0
The Connection Detect Register provides a means to determine the status of the DAC outputs and the DVI hot plug detect pin. The status bits, DACT[2:0] correspond to the termination of the three DAC outputs. However, the values contained in these STATUS BITS ARE NOT VALID until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The detection sequence works as follows: 1) Set the power management register to enable all DAC's. 2) Set the SENSE bit to a 1. This forces a constant output from the DAC's. Note that during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted. 3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and the reference value. During this step, each of the four status bits corresponding to individual DAC outputs will be set if they are NOT CONNECTED. 4) Read the status bits. The status bits, DACT[2:0] now contain valid information which can be read to determine which outputs are connected to a TV. Again, a "0" indicates a valid connection, a "1" indicates an unconnected output. Bit 5 of register CD can be read at any time to determine the level of the hot plug detect pin. When the hot plug detect pin changes state, and the DVI output is selected, the TLDET* output pin will be pulled low signifying a change in the DVI termination. At this point, the HPIR bit in register 1Eh should be set high, then low to reset the hot plug detect circuit. Bit 7 of register CD enables the hot plug interrupt detection signal output from the GPIO[1] pin. A value of `1' allows the hot plug detect circuit to pull the GPIO[1] / TLDET* pin low when a change of state has taken place on the hot plug detect pin. A value of `0' disables the interrupt signal. The GOENB1 control bit in register 1Eh should be set to `1' when HPIE2 is set to `1'.
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DAC Control Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
CH7301A
DC 21h 6
7 6 Reserved Reserved R/W R/W 0 0
5
4 3 SYNCO1 SYNCO0 R/W R/W 0 0
2 DACG1 R/W 0
1 DACG0 R/W 0
0 DACBP R/W 0
Bit 0 of register DC selects the DAC bypass mode. A value of `1' outputs the incoming data directly at the DAC[2:0] outputs. Bits 2-1 of register DC control the DAC gain. DACG0 should be set low for NTSC and PAL-M video standards, and high for PAL and NTSC-J video standards. DACG1 should be low when the input data format is RGB (IDF = 0-3), and high when the input data format is YCrCb (IDF = 4). Bits 4-3 of register DC select the signal to be output from the C/H Sync pin according to Table 9 below.
Table 9: Composite / Horizontal Sync Output
SYNCO[1:0] 00 01 10 11 C/H Sync Output No Output VGA Horizontal Sync TV Composite Sync (Not Valid) TV Horizontal Sync (Not Valid)
Buffered Clock Output Register
Symbol: Address: Bits:
BCO 22h 8
BIT: SYMBOL: TYPE: DEFAULT:
7 6 5 Reserved Reserved Reserved R/W R/W R/W 0 0 0
4 BCOEN R/W 0
3 BCOP R/W 0
2 BCO2 R/W 0
1 BCO1 R/W 0
0 BCO0 R/W 0
Bits 2-0 of register BCO select the signal output at the BCO pin, according to Table 10 below:
Table 10: BCO Output Signal
BCO[2:0] 000 001 010 011 Buffered Clock Output (Not Valid) (Not Valid) (Not Valid) (Not Valid) BCO[2:0] 100 101 110 111 Buffered Clock Output (Not Valid) (Not Valid) VGA Vertical Sync (Not Valid)
Bit 3 of register BCO selects the polarity of the BCO output. A value of `1' does not invert the signal at the output pad. Bit 4 of register BCO enables the BCO output. When BCOEN is high, the BCO pin will output the selected signal. When BCOEN is low, the BCO pin will be held in tri-state mode.
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DVI Control Input Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
CH7301A
TCTL 31h 8
7 TPPD3 R/W 1
6 TPPD 2 R/W 0
5 TPPD 1 R/W 0
4 TPPD 0 R/W 0
3 CTL3 R/W 0
2 CTL2 R/W 0
1 CTL1 R/W 0
0 CTL0 R/W 0
Bits 3-0 of register TCTL set the DVI control inputs applied to the green and red channels during sync intervals. It is recommended to leave these controls at the default value. Bits 7-4 of register TCTL control the DVI PLL phase detector. The default value is recommended.
DVI PLL VCO Control Register
Symbol: Address: Bits:
TVCO 32h 8
BIT: SYMBOL: TYPE: DEFAULT:
7 6 5 4 3 2 1 TPVCO7 TPVCO6 TPVCO5 TPVCO4 TPVCO3 TPVCO2 TPVCO1 R/W R/W R/W R/W R/W R/W R/W 1 0 1 0 0 0 0
0 TPVCO0 R/W 0
Register TVCO controls the state of the DVI PLL VCO, and should be set according to the following tables.
DVI PLL Charge Pump Control Register
Symbol: Address: Bits:
TPCP 33h 5
BIT: SYMBOL: TYPE: DEFAULT:
7 DVID2 R/W 1
6 DVID1 R/W 1
5 DVID0 R/W 1
4 3 2 DVII Reserved Reserved R/W R/W R/W 0 0 1
1 TPCP1 R/W 0
0 TPCP0 R/W 0
Bits 1-0 of register TPCP control the DVI PLL charge pump. The default value is recommended. Bits 3-2 of register TPCP are reserved bits, and should be left at the default value. Bit 4 of register TPCP inverts the DVI outputs. A value of 1 inverts the outputs. A value of 0 is recommended. Bits 7-5 of register TPCP control the DVI transmitter output drive level. The default value is recommended for DVI applications.
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DVI PLL Supply Control Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
CH7301A
TPVT 35h 5
7 6 Reserved Reserved R/W R/W 0 0
5 TPVT5 R/W 1
4 TPVT4 R/W 1
3 TPVT3 R/W 0
2 TPVT2 R/W 0
1 TPVT1 R/W 0
0 TPVT0 R/W 0
Bits 5-0 of register TPVT control the DVI PLL supply voltage. The default value is recommended. Bits 7-6 of register TPVT are reserved bits, and should be left at the default value. DVI PLL Filter Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
TPF 36h 8
7 TPLPF3 R/W 0
6 TPLPF2 R/W 0
5 TPLPF1 R/W 0
4 3 2 1 TPLPF0 Reserved Reserved Reserved R/W R/W R/W R/W 0 0 0 0
0 Reserved R/W 0
Bits 3-0 of register TPT are reserved bits, and should be left at the default value. Bits 7-4 of register TPT control the DVI PLL low pass filter. The default value is recommended.
Test Pattern Register
Symbol: Address: Bits:
TSTP 48h 5
BIT: SYMBOL: TYPE: DEFAULT:
7
6
5
4 3 ResetIB ResetDB R/W R/W 1 1
2 RSA R/W 0
1 TSTP1 R/W 0
0 TSTP0 R/W 0
Bits 1-0 of register TSTP control the test pattern generation block. This test pattern can be used for both the DVI output and the TV Output. The pattern generated is determined by Table 11 below.
Table 11: Test Pattern Control
TSTP[1:0] 00 01 1 Buffered Clock Output No test pattern - Input data is used Color Bars Horizontal Luminance Ramp
Bit 2 of register TSTP is a test control, and should be left at the default value.
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CH7301A
Bit 3 of register TSTP controls the datapath reset signal. A value of `0' holds the datapath in a reset condition, while a value of `1', places the datapath in normal mode. The datapath is also reset at power on by an internally generated power on reset signal. Bit 4 of register TSTP controls the IIC reset signal. A value of `0' holds the IIC registers in a reset condition, while a value of `1', places the IIC registers in normal mode. The IIC registers are also reset at power on by an internally generated power on reset signal. Power Management Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
PM 49h 8
7 DVIP R/W 0
6 DVIL R/W 0
5 4 3 2 1 TV Reserved DACPD2 DACPD1 DACPD0 R/W R/W R/W R/W R/W 0 0 0 0 0
0 FPD R/W 1
Register TSTP controls which circuitry within the CH7301 is operating, according to Table 12 below.
Table 12: Power Management
Circuit Block DVI PLL DVI Encode, Serialize and Transmitter VGA to TV Encoder DAC 2 DAC 1 DAC 0 TV PLL, P-Out and BCO pins Is Operational When DVIP = 1 & FPD != 1 DVIL = 1 & FPD != 1 N/A DACPD2 != 1 & FPD != 1 DACPD1 != 1 & FPD != 1 DACPD0 != 1 & FPD != 1 FPD != 1
Version ID Register
Symbol: Address: Bits:
VID 4Ah 8
BIT: SYMBOL: TYPE: DEFAULT:
7 VID7 R MV
6 VID6 R 0
5 VID5 R 0
4 VID4 R 0
3 VID3 R 0
2 VID2 R 0
1 VID1 R 0
0 VID0 R 0
Register VID is a read only register containing the version ID number of the CH7301. The MV default is `1' when the CH7301 is bonded out with Macrovision enabled, and `0' when the CH7301 is bonded out with Macrovision disabled.
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Device ID Register Symbol: Address: Bits:
BIT: SYMBOL: TYPE: DEFAULT:
CH7301A
DID 4Bh 8
7 DID7 R TBD
6 DID6 R TBD
5 DID5 R TBD
4 DID4 R TBD
3 DID3 R TBD
2 DID2 R TBD
1 DID1 R TBD
0 DID0 R TBD
Register DID is a read only register containing the device ID number of the CH7301.
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Electrical Specifications
Table 13. Absolute Maximum Ratings
Symbol Description
DVDD, AVDD, TVDD, VDD relative to GND Input voltage of all digital pins1
CH7301A
Min - 0.5 GND - 0.5
Typ
Max 5.0 VDD + 0.5
Units V V Sec
TSC T AMB TSTOR TJ TVPS
Analog output short circuit duration Ambient operating temperature Storage temperature Junction temperature Vapor phase soldering (one minute)
Indefinite - 55 - 65 85 150 150 220
C C C C
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods my affect reliability. 2. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than 0.5V can induce destructive latch. Table 14. Recommended Operating Conditions
Symbol VDD AVDD DVDD TVDD, DVDDV RL Description
DAC power supply voltage Analog supply voltage Digital supply voltage Digital supply voltage (P-OUT pin) Output load to DAC outputs
Min
3.1 3.1 3.1 1.1
Typ
3.3 3.3 3.3 1.8 37.5
Max
3.6 3.6 3.6 3.6
Units
V V V
V
Table 15. Electrical Characteristics (Operating Conditions: TA = 0o C - 70oC, VDD = 5V 5%)
Video D/A resolution Full scale output current Video level error VDD & AVDD current DVDD, TVDD (3.3V) current DVDD2 (1.8V) current (15pF load)
10
10 33.89
10 10
Bits mA % mA mA mA
90 TBD 4
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CHRONTEL
Table 16. Digital Inputs / Outputs
Symbol
V SDOL V IICIH V IICIL V DATAIH VDATAIL V P-OUTOH V P-OUTOL
CH7301A
Description
SD Output Low Voltage SD Input High Voltage SD Input Low Voltage D[0-11] Input High Voltage D[0-11] Input Low Voltage P-OUT Output High Voltage P-OUT Output Low Voltage
Test Condition
IOL = 2.0 mA
Min
Typ
Max
0.4
Unit
V V V V V V
2.7 GND-0.5 Vref-0.25 GND-0.5 IOL = - 400 A IOL = 3.2 mA DVDDV-0.2
DVDD + 0.5 1.4 DVDD+0.5 Vref+0.25
0.2
V
Note:
V IIC -refers to I C pins SD and SC. VDATA - refers to all digital pixel and clock inputs. 2 VSD - refers to I C pin SD as an output. VP-OUT - refers to pixel data output Time - Graphics.
2
28
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CHRONTEL
Mechanical Package Information
CH7301A
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CHRONTEL
CH7301A
ORDERING INFORMATION
Part number CH7301A-T CH7301A-T-A CH7301A-T-B Package type LQFP LQFP LQFP Number of pins 64 64 64 Voltage supply 3.3V 3.3V 3.3V Speed grade 115MHz 135MHZ 165MHZ
Chrontel
2210 O'Toole Avenue San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com
(c)1998 Chrontel, Inc. All Rights Reserved. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. Printed in the U.S.A.
201-0000--036 Rev 1.1, 3/20/2000
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